Display panel

ABSTRACT

A display panel for an organic light emitting display including a plurality of anode electrodes and a cathode electrode that is supplied with a predetermined voltage and includes a first portion facing the anode electrodes and a second portion receiving the predetermined voltage and having a different cross section than the first portion. A plurality of light emitting members is arranged between the anode electrodes and the cathode electrode, and a conductive line transmits the predetermined voltage and contacts the second portion of the cathode electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 10-2004-0051426, filed on Jul. 2, 2004, which is herebyincorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display panel and in particular, to apanel for an organic light emitting diode display.

2. Discussion of the Background

Generally, an organic light emitting diode (OLED) display is a selfemissive display device that displays images by exciting an emissiveorganic material to emit light. A light emitting element of an OLEDdisplay includes an anode (hole injection electrode), a cathode(electron injection electrode), and an organic light emission layerinterposed therebetween. When holes and electrons are injected into thelight emission layer, they recombine and emit light when transitioningfrom an excited state to a ground state. The organic light emissionlayer may further include one or more of an electron transport layer(ETL) and a hole transport layer (HTL) as well as an electron injectinglayer (EIL) and a hole injecting layer (HIL) for enhancing the lightemission.

The OLED display includes a plurality of pixels, and each pixel includesan anode, a cathode, and a light emission layer. The pixels may bearranged in a matrix, and they may be driven in passive matrix (orsimple matrix) addressing or active matrix addressing.

The passive matrix OLED display includes a plurality of anode lines, aplurality of cathode lines intersecting the anode lines, and a pluralityof pixels, each including a light emission layer. Selecting an anodeline and a cathode line causes a pixel located at the intersection ofthe selected signal lines to emit light.

The active matrix (AM) OLED display includes a plurality of pixels, andeach pixel may include a switching transistor, a driving transistor, anda storage capacitor as well as an anode, a cathode, and a light emissionlayer. The AM OLED display further includes a plurality of gate linestransmitting gate signals and a plurality of data lines transmittingdata voltages. The switching transistor is coupled to a gate line and adata line, and it transmits the data voltage from the data line inresponse to the gate signal from the gate line. The driving transistorreceives the data voltage from the switching transistor and drives acurrent having a magnitude corresponding to the data voltage. Thecurrent from the driving transistor enters the light emission layer tocause light emission having an intensity depending on the current. Thestorage capacitor is coupled between the data voltage and a supplyvoltage to maintain their voltage difference. The gray scaling of the AMOLED display is accomplished by controlling the data voltages to adjustthe current driven by the driving transistor. The OLED displayrepresents colors by providing red, green and blue light emissionlayers.

Additionally, OLED displays may be top emission and bottom emissiondisplays depending on a light emitting direction. The top emission OLEDdisplay includes a transparent cathode, which is usually made of indiumtin oxide (ITO) or indium zinc oxide (IZO), and an opaque anode.Conversely, the bottom emission OLED display includes an opaque cathodeand a transparent anode. The relative positions of the anode and thecathode may be altered if required.

The cathode is supplied with a common voltage through another conductor,and the contact resistance between the cathode and the conductor may behigh.

SUMMARY OF THE INVENTION

The present invention provides an OLED device that may have decreasedcontact resistance between a common electrode and a common voltage line.

Additional features of the invention will be set forth in thedescription which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention.

The present invention discloses a display panel for an organic lightemitting display including a plurality of anode electrodes, and acathode electrode that is supplied with a predetermined voltage andincludes a first portion facing the anode electrodes and a secondportion receiving the predetermined voltage and having a differentcross-section than the first portion. A plurality of light emittingmembers is arranged between the anode electrodes and the cathodeelectrode, and a conductive line transmits the predetermined voltage andcontacts the second portion of the cathode electrode.

The present invention also discloses a display panel for an organiclight emitting display including a plurality of anode electrodes, aplurality of light emitting members arranged on the anode electrodes,respectively, a metal layer including a first portion arranged on thelight emitting members and a second portion spaced apart from the lightemitting members, and a conductive line coupled to the second portion ofthe metal layer. The conductive line is arranged on a layer that isbeneath a layer that the light emitting members are arranged on.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention.

FIG. 1 is a block diagram of an OLED display according to an embodimentof the present invention.

FIG. 2 is an equivalent circuit diagram of a pixel of an OLED displayaccording to an embodiment of the present invention.

FIG. 3 is a schematic plan view of a display panel for an OLED displayaccording to an embodiment of the present invention.

FIG. 4 is a section view of the display panel taken along line IV-IV′ ofFIG. 3.

FIG. 5 is a layout view of a pixel and signal lines on the display panelof FIG. 3.

FIG. 6 and FIG. 7 are sectional views of the pixel and the signal linestaken along lines VI-VI′ and VII-VII′ of FIG. 5, respectively.

FIG. 8 is a schematic diagram of an organic light emitting elementaccording to an embodiment of the present invention.

FIGS. 9, 11, 13,15,17, 19, 21, 23 and 25 are layout views of the displaypanel shown in FIGS. 3, 4, 5, 6, and 7 in intermediate steps of amanufacturing method thereof according to an embodiment of the presentinvention.

FIG. 10A and FIG. 10B are sectional views of the display panel takenalong lines XA-XA′ and XB-XB′ of FIG. 9, respectively, and FIG. 10C is asectional view of the display panel taken along line IV-IV′ of FIG. 3 atthis step.

FIG. 12A and FIG. 12B are sectional views of the display panel takenalong lines XIIA-XIIA′ and XIIB-XIIB′ of FIG. 11, respectively, and FIG.12C is a sectional view of the display panel taken along line IV-IV′ ofFIG. 3 at this step.

FIG. 14A and FIG. 14B are sectional views of the display panel takenalong lines XIVA-XIVA′ and XIVB-XIVB′ of FIG. 13, respectively, and FIG.14C is a sectional view of the display panel taken along line IV-IV′ ofFIG. 3 at this step.

FIG. 16A and FIG. 16B are sectional views of the display panel takenalong lines XVIA-XVIA′ and XVIB-XVIB′ of FIG. 15, respectively, and FIG.16C is a sectional view of the display panel taken along line IV-IV′ ofFIG. 3 at this step.

FIG. 18A and FIG. 18B are sectional views of the display panel takenalong lines XVIIIA-XVIIIA′ and XVIIIB-XVIIIB′ of FIG. 17, respectively,and FIG. 18C is a sectional view of the display panel taken along lineIV-IV′ of FIG. 3 at this step.

FIG. 20A and FIG. 20B are sectional views of the display panel takenalong lines XXA-XXA′ and XXB-XXB′ of FIG. 19, respectively, and FIG. 20Cis a sectional view of the display panel taken along line IV-IV′ of FIG.3 at this step.

FIG. 22A and FIG. 22B are sectional views of the display panel takenalong lines XXIIA-XXIIA′ and XXIIB-XXIIB′ of FIG. 21, respectively, andFIG. 22C is a sectional view of the display panel taken along lineIV-IV′ of FIG. 3 at this step.

FIG. 24A and FIG. 24B are sectional views of the display panel takenalong lines XXIVA-XXIVA′ and XXIVB-XXIVB′ of FIG. 23, respectively, andFIG. 24C is a sectional view of the display panel taken along lineIV-IV′ of FIG. 3 at this step.

FIG. 26A and FIG. 26B are sectional views of the display panel takenalong lines XXVIA-XXVIA′ and XXVIB-XXVIB′ of FIG. 25, respectively, andFIG. 26C is a sectional view of the display panel taken along lineIV-IV′ of FIG. 3 at this step.

FIG. 27A and FIG. 27B are sectional views of the display panel takenalong lines XXVIA-XXVIA′ and XXVIB-XXVIB′ of FIG. 25, respectively, andillustrate a step following the step shown in FIG. 26A and FIG. 26B, andFIG. 27C is a sectional view of the display panel taken along lineIV-IV′ of FIG. 3 at this step.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. The present invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc.are exaggerated for clarity. Like numerals refer to like elementsthroughout. It will be understood that when an element such as a layer,film, region or substrate is referred to as being “on” another element,it can be directly on the other element or intervening elements may alsobe present. In contrast, when an element is referred to as being“directly on” another element, there are no intervening elementspresent.

Now, display panels for an OLED display and manufacturing methodsthereof according to embodiments of the present invention will bedescribed with reference to accompanying drawings.

FIG. 1 is a block diagram of an OLED display according to an embodimentof the present invention, and FIG. 2 is an equivalent circuit diagram ofa pixel of an OLED display according to an embodiment of the presentinvention.

Referring to FIG. 1, an OLED display according to an embodiment of theinvention includes a display panel 300 and two drivers including ascanning driver 400 and a data driver 500, which are coupled to thedisplay panel 300.

The display panel 300 includes a plurality of signal lines, and aplurality of pixels PX are coupled thereto and arranged substantially ina matrix.

The signal lines include a plurality of scanning lines G₁-G_(n) fortransmitting scanning signals and a plurality of data lines D₁-D_(m) fortransmitting data signals. The scanning lines G₁-G_(n) extendsubstantially in a row direction and substantially parallel to eachother, while the data lines D₁-D_(m) extend substantially in a columndirection and substantially parallel to each other.

Referring to FIG. 2, for example, each pixel PX may be coupled to ascanning line G_(i) and a data line D_(j) and may include an organiclight emitting element LD, a driving transistor Qd, a capacitor Cst, anda switching transistor Qs.

The driving transistor Qd has a control terminal coupled to theswitching transistor Qs, an input terminal coupled to a driving voltageVp, and an output terminal coupled to the light emitting element LD.

The light emitting element LD has an anode coupled to the outputterminal of the driving transistor Qd and a cathode coupled to a commonvoltage Vcom. The common voltage Vcom may be less than the drivingvoltage Vp and it may be a ground voltage, for example. The lightemitting element LD emits light at an intensity depending on an outputcurrent of the driving transistor Qd, and the output current of thedriving transistor Qd depends on the voltage between the controlterminal and the input terminal of the driving transistor Qd.

The switching transistor Qs has a control terminal coupled to thescanning line G_(i), an input terminal coupled to the data line D_(j),and an output terminal coupled to the control terminal of the drivingtransistor Qd. The switching transistor Qs transmits the data signalfrom the data line D_(j) to the driving transistor Qd in response to thescanning signal from the scanning line G_(i).

As shown in FIG. 2, the switching transistor Qs is an N-channel fieldeffect transistor (FET), while the driving transistor Qd is a P-channelFET. However, their types may be exchanged or both may be N channel FETsor P channel FETs. In this case, the connections between the transistorsQs and Qd and the light emitting element LD may be modified.

The transistors Qs and Qd may include polycrystalline silicon(polysilicon) or amorphous silicon (a-Si).

The capacitor Cst is coupled between the control terminal and the inputterminal of the driving transistor Qd. The capacitor Cst charges andmaintains a voltage corresponding to the data signal applied to thecontrol terminal of the driving transistor Qd.

Referring to FIG. 1 again, the scanning driver 400 is coupled to thescanning lines G₁-G_(n) of the display panel 300 and synthesizes agate-on voltage Von for turning on the switching transistors Qs and agate-off voltage Voff for turning off the switching transistors Qs togenerate scanning signals to apply to the scanning lines G₁-G_(n).

The data driver 500 is coupled to the data lines D₁-D_(m) of the displaypanel 300 and applies data signals to the data lines D₁-D_(m).

The scanning driver 400 and the data driver 500 may be implemented as anintegrated circuit (IC) chip mounted on the display panel 300 or on aflexible printed circuit (FPC) film in a tape carrier package (TCP),which are attached to the display panel 300. Alternatively, they may beintegrated into the display panel 300.

Now, a structure of a display panel for an OLED display according to anembodiment of the present invention will be described in detail withreference to FIGS. 3-8, as well as FIG. 1 and FIG. 2.

FIG. 3 is a schematic plan view of a display panel for an OLED displayaccording to an embodiment of the present invention, FIG. 4 is a sectionview of the display panel taken along line IV-IV′ of FIG. 3, FIG. 5 is alayout view of a pixel and signal lines on the display panel shown inFIG. 3, FIG. 6 and FIG. 7 are sectional views of the pixel and thesignal lines taken along the lines VI-VI′ and VII-VII′ of FIG. 5,respectively, and FIG. 8 is a schematic diagram of an organic lightemitting element according to an embodiment of the present invention.

Referring to FIG. 3, a display panel 300 according to an embodiment ofthe present invention includes a display area DA (enclosed by a dottedrectangle) and a peripheral area PA arranged outside the display areaDA. The display area DA comprises a plurality of pixels PX.

A common electrode 270, which serves as cathodes of organic lightemitting elements LD, is also provided on the display panel 300. Thecommon electrode 270 covers the display area DA and includes a contactportion B arranged in the peripheral area PA for receiving a commonvoltage Vcom. The contact portion B of the common electrode 270 iscoupled to a common voltage line 278, which includes a common voltagepad 279 for receiving the common voltage Vcom from an external device.

A plurality of signal lines including scanning lines G₁-G_(n) and datalines D₁-D_(n) are also provided on the display panel 300. The signallines include portions arranged in the display area DA as well as endportions arranged in the peripheral area to receive signals includingscanning signals and data signals.

The scanning driver 400 and the data driver 500 may be arranged outsidethe display panel 300, arranged on the peripheral area PA, or integratedinto the peripheral area PA of the display panel 300 along with thepixels and the signal lines.

Next, referring to FIG. 3, FIG. 4, FIG. 5, FIG. 6 and FIG. 7, a detailedlayered structure of the display panel will be described.

A blocking layer 111, which may be made of silicon oxide or siliconnitride, is formed on an insulating substrate 110, which may be made oftransparent glass. The blocking layer 111 may have a dual-layeredstructure.

A plurality of semiconductor islands 151 a and 151 b, which may be madeof polysilicon or a-Si, are formed on the blocking film 111. Eachsemiconductor island 151 a and 151 b may include a plurality ofextrinsic regions containing an N-type or Ptype conductive impurity andat least one intrinsic region hardly containing conductive impurity.

Regarding the semiconductor island 151 a for the switching thin filmtransistor (TFT) Qs, the extrinsic regions include a first source region153 a, an intermediate region 1535, and a first drain region 155 a,which are doped with an N-type impurity and separated from one another,and the intrinsic regions include a pair of (first) channel regions 154a 1 and 154 a 2 disposed between the extrinsic regions 153 a, 1535 and155 a.

Concerning the semiconductor island 151 b for the driving TFT Qd, theextrinsic regions include a second source region 153 b and a seconddrain region 155 b, which are doped with a P-type impurity and separatedfrom one another, and the intrinsic region includes a channel region 154b arranged between the second source region 153 b and the second drainregion 155 b. The second source region 153 b extends to form a storageelectrode region 157.

The extrinsic regions may further include lightly doped regions (notshown) disposed between the channel regions 154 a 1, 154 a 2 and 154 band the source and the drain regions 153 a, 155 a, 153 b and 155 b. Thelightly doped regions may be substituted with offset regions thatcontain substantially no impurity.

Alternatively, the extrinsic regions 153 a and 155 a of the firstsemiconductor islands 151 a may be doped with P-type impurity, while theextrinsic regions 153 b and 155 b of the second semiconductor islands151 b may be doped with N-type impurity, depending on drivingconditions. The conductive impurity may include a P-type impurity suchas boron (B) and gallium (Ga) and an N-type impurity such as phosphorous(P) and arsenic (As).

The semiconductor islands 151 a and 151 b may be made of a-Si. In thiscase, there are no impurity regions, and ohmic contacts may be formed onthe semiconductor islands 151 a and 151 b to improve contactcharacteristics between semiconductor islands 151 a and 151 b and othermetal layers.

A gate insulating layer 140, which may be made of silicon oxide orsilicon nitride, is formed on the semiconductor islands 151 a and 151 band the blocking film 111.

A plurality of gate conductors including a plurality of gate lines 121,including a plurality of pairs of first gate electrodes 124 a, and aplurality of second gate electrodes 124 b are formed on the gateinsulating layer 140.

The gate lines 121, which transmit gate signals, extend substantially ina transverse direction. Each pair of first gate electrodes 124 aprotrudes upward from the gate line 121, and they cross the firstsemiconductor islands 151 a such that they overlap the pair of the firstchannel regions 154 a 1 and 154 a 2. Each gate line 121 may include anexpanded end portion having a large area for coupling with another layeror an external driving circuit. The gate lines 121 may be directlyconnected to a gate driving circuit for generating the gate signals,which may be integrated on the substrate 110.

The second gate electrodes 124 b are separate from the gate lines 121and they cross the second semiconductor islands 151 b such that theyoverlap the second channel regions 154 b. The second gate electrodes 124b extend to form storage electrodes 127 that overlap the storageelectrode regions 157 of the second semiconductor islands 151 b, therebyforming storage capacitors Cst.

The gate conductors 121 and 124 b may be made of low resistivitymaterial including, for example, Al containing metal such as Al and Alalloy (e.g. Al—Nd), Ag containing metal such as Ag and Ag alloy, and Cucontaining metal such as Cu and Cu alloy. The gate conductors 121 and124 b may have a multi-layered structure including two films havingdifferent physical characteristics. In this case, one of the two filmsmay be made of low resistivity metal including Al containing metal, Agcontaining metal, and Cu containing metal for reducing signal delay orvoltage drop in the gate conductors 121 and 124 b. The other film may bemade of material such as Cr, Mo and Mo alloy, Ta or Ti, which has goodphysical, chemical, and electrical contact characteristics with othermaterials such as indium tin oxide (ITO) or indium zinc oxide (IZO).Examples of the layered structure include a lower Cr film and an upperAl—Nd alloy film and a lower Al film and an upper Mo film.

Additionally, the lateral sides of the gate conductors 121 and 124 b maybe inclined relative to a surface of the substrate 110 at an angle ofabout 30-80 degrees.

An interlayer insulating layer 160 is formed on the gate conductors 121and 124 b. The interlayer insulating layer 160 may be made ofphotosensitive organic material having a good flatness characteristic,low dielectric insulating material such as a-Si:C:O and a-Si:O:F formedby plasma enhanced chemical vapor deposition (PECVD), or inorganicmaterial such as silicon nitride and silicon oxide.

The interlayer insulating layer 160 has a plurality of contact holes 164exposing the second gate electrodes 124 b. Additionally, the interlayerinsulating layer 160 and the gate insulating layer 140 have a pluralityof contact holes 163 a, 163 b, 165 a and 165 b exposing the sourceregions 153 a and 153 b and the drain regions 155 a and 155 b,respectively.

A plurality of data conductors including a plurality of data lines 171,a plurality of driving voltage lines 172, a plurality of first andsecond drain electrodes 175 a and 175 b, and a common voltage line 278are formed on the interlayer insulating film 160.

The data lines 171, which transmit data signals, extend substantially inthe longitudinal direction and cross the gate lines 121. Each data line171 includes a plurality of first source electrodes 173 a, which arecoupled to the first source regions 153 a through the contact holes 163a. Each data line 171 may include an expanded end portion having a largearea for coupling with another layer or an external driving circuit. Thedata lines 171 may be directly connected to a data driving circuit forgenerating the data signals, which may be integrated on the substrate110.

The driving voltage lines 172, which transmit driving voltages for thedriving TFT Qd, extend substantially in the longitudinal direction andcross the gate lines 121. Each driving voltage line 172 includes aplurality of second source electrodes 173 b, which are coupled to thesecond source regions 153 b through the contact holes 163 b. The drivingvoltage lines 172 may be coupled to each other.

The first drain electrodes 175 a are separated from the data lines 171and the driving voltage lines 172 and are coupled to the first drainregions 155 a through the contact holes 165 a and to the second gateelectrodes 124 b through the contact holes 164.

The second drain electrodes 175 b are separated from the data lines 171and the driving voltage lines 172 and are coupled to the second drainregions 155 b through the contact holes 165 b.

The common voltage line 278 includes a common voltage pad 279 arrangednear an upper edge of the substrate 110 as shown in FIG. 3. The commonvoltage line 278 may be formed of the same layer as the gate lines 121.

The data conductors 171, 172, 175 a, 175 b and 278 may be made ofrefractory metal including Cr, Mo, Ti, Ta or alloys thereof. They mayhave a multi-layered structure including a low resistivity film and agood contact film. An example of the multi-layered structure includes adouble-layered structure of a lower Cr film and an upper Al (alloy)film, a double-layered structure of a lower Mo (alloy) film and an upperAl (alloy) film, and a triple-layered structure of a lower Mo film, anintermediate Al film, and an upper Mo film.

Like the gate conductors 121 and 124 b, the data conductors 171, 172,175 a, 175 b and 278 have inclined edge profiles at an angle of about30-80 degrees to the substrate.

A passivation layer 180 is formed on the data conductors 171, 172, 175a, 175 b and 278. The passivation layer 180 may be made ofphotosensitive organic material having a good flatness characteristic,low dielectric insulating material such as a-Si:C:O and a-Si:O:F formedby PECVD, or inorganic material such as silicon nitride and siliconoxide.

The passivation layer 180 has a plurality of contact holes 185 and 188exposing the second drain electrodes 175 b and the common voltage line278, respectively. The passivation layer 180 may further include aplurality of contact holes (not shown) exposing end portions of the datalines 171, and the passivation layer 180 and the interlayer insulatinglayer 160 may have a plurality of contact holes (not shown) exposing endportions of the gate lines 121. When the common voltage line 278 isarranged under the interlayer insulating layer 160, the contact holes188 may penetrate the interlayer insulating layer 160.

A plurality of pixel electrodes 190 and a contact assistant 88 may beformed on the passivation layer 180.

The pixel electrodes 190 may serve as anodes of light emitting elementsLD shown in FIG. 2, and they may be coupled to the second drainelectrodes 175 b through the contact holes 185. The pixel electrodes 190and the contact assistant 88 may be made of a transparent conductor suchas ITO or IZO. However, the pixel electrode 190 may be made of an opaquereflective conductor such as Al, Ag, Ca, Ba and Mg.

The contact assistant 88 is coupled to the common voltage line 278through the contact holes 188 to cover the exposed portion of the commonvoltage line 278. The contact assistant 88 may be omitted, or more thanone contact assistant may be formed.

A plurality of contact assistants or connecting members (not shown) maybe also formed on the passivation layer 180 such that they are connectedto the exposed end portions of the gate lines 121, the data lines 171,or the common voltage pad 279.

A partition 360, which separates pixels of the OLED display, is formedon the passivation layer 180 and the pixel electrodes 190. The partition360 surrounds the pixel electrodes 190 to define openings 365 to befilled with organic light emitting material. The partition 360 has aplurality of contact holes 368 exposing the contact assistants 88, andit may be made of organic or inorganic insulating material.

A plurality of light emitting members 370 are formed on the pixelelectrodes 190 and disposed in the openings 365 defined by the partition360. The light emitting members 370 may be made of organic materialemitting primary-color lights such as red, green and blue lights. Thered, green and blue light emitting members 370 are periodicallyarranged.

A common electrode 270 including a lower electrode 271 and an upperelectrode 272 is formed on the light emitting members 370 and thepartition 360. The common electrode 270 is supplied with the commonvoltage Vcom.

The lower electrode 271 may be made of an insulator such as LiF or analkali, or an alkali earth metal such as Ba, Ca, or Li, while the upperelectrode 272 may be made of low resistivity metal such as Al, Ag, ortheir alloys. The lower electrode 271, which may contact the lightemitting members 370, may have a low work function such that the lowerelectrode 271 facilitates the injection of electrons into the lightemitting members 370. The upper electrode 272 may be made of lowresistivity material resistant to oxidation such that the upperelectrode 272 protects the lower electrode 271 and reduces thedistortion of the common voltage Vcom.

As FIG. 3 and FIG. 4 show, the upper electrode 272 includes a contactportion B contacting the contact assistant 88 through the contact holes368, and the lower electrode 271 does not contact the contact assistant88. This structure reduces the contact resistance between the commonelectrode 270 and the contact assistant 88 or the common voltage line278. In detail, metal having a low work function such as Ba or Ca may beeasily melted by a small amount of heat such as that generated at thecontact portion B, thereby increasing the contact resistance.Additionally, an insulator such as LiF also increases the contactresistance. With the above-described structure, the upper electrode 272contacts the contact assistant 88, but the lower electrode 271 does not.Accordingly, the contact resistance between the common electrode 270 andthe common voltage line 278 may be decreased.

In the above-described OLED display, a switching TFT Qs comprises afirst semiconductor island 151 a, a first gate electrode 124 a connectedto the gate line 121, a first source electrode 173 a connected to thedata line 171, and a first drain electrode 175 a. Additionally, adriving TFT comprises a second semiconductor island 151 b, a second gateelectrode 124 b connected to the first drain electrode 175 a, a secondsource electrode 173 b connected to the driving voltage line 172, and asecond drain electrode 175 b connected to a pixel electrode 190.Furthermore, a storage electrode region 157 coupled to a second sourceregion 153 b and a storage electrode 127 coupled to a second gateelectrode 124 b form a storage capacitor Cst. The exemplary TFTs Qs andQd shown in FIGS. 5-7 are referred to as “top gate TFTs” since the gateelectrodes 124 a and 124 b are arranged on the semiconductors 151 a and151 b.

The organic light emitting member 370 may have a multilayered structureas shown in FIG. 8. The organic light emitting member 370 includes atleast an emitting layer EML, and it may further include auxiliary layersto improve the light emission efficiency of the emitting layer EML. Theauxiliary layers may include an electron transport layer ETL and a holetransport layer HTL for improving the balance of electrons and holes,and an electron injecting layer EIL and a hole injecting layer HIL forimproving the injection of electrons and holes. The lower electrode 271of the common electrode 270 may serve as the electron injection layerEIL.

Now, a method of manufacturing the display panel shown in FIGS. 3-8 isdescribed below with reference to FIGS. 9-27C as well as FIGS. 3-8.

FIG. 9, FIG. 11, FIG. 13, FIG. 15, FIG. 17, FIG. 19, FIG. 21, FIG. 23and FIG. 25 are layout views of the display panel of FIGS. 3-8 inintermediate steps of a manufacturing method thereof according to anembodiment of the present invention. FIG. 10A and FIG. 10B are sectionalviews of the display panel taken along lines XA-XA′ and XB-XB′ of FIG.9, respectively, and FIG. 10C is a sectional view of the display paneltaken along line IV-IV′ of FIG. 3 at this step. FIG. 12A and FIG. 12Bare sectional views of the display panel taken along lines XIIA-XIIA′and XIIB-XIIB′ of FIG. 11, respectively, and FIG. 12C is a sectionalview of the display panel taken along line IV-IV′ of FIG. 3 at thisstep. FIG. 14A and FIG. 14B are sectional views of the display paneltaken along lines XIVA-XIVA′ and XIVB-XIVB′ of FIG. 13, respectively,and FIG. 14C is a sectional view of the display panel taken along lineIV-IV′ of FIG. 3 at this step. FIG. 16A and FIG. 16B are sectional viewsof the display panel taken along lines XVIA-XVIA′ and XVIB-XVIB′ of FIG.15, respectively, and FIG. 16C is a sectional view of the display paneltaken along line IV-IV′ of FIG. 3 at this step. FIG. 18A and FIG. 18Bare sectional views of the display panel taken along linesXVIIIA-XVIIIA′ and XVIIIB-XVIIIB′ of FIG. 17, respectively, and FIG. 18Cis a sectional view of the display panel taken along line IV-IV′ of FIG.3 at this step. FIG. 20A and FIG. 20B are sectional views of the displaypanel taken along the lines XXA-XXA′ and XXB-XXB′ of FIG. 19,respectively, and FIG. 20C is a sectional view of the display paneltaken along line IV-IV′ of FIG. 3 at this step. FIG. 22A and FIG. 22Bare sectional views of the display panel taken along lines XXIIA-XXIIA′and XXIIB-XXIIB′ of FIG. 21, respectively, and FIG. 22C is a sectionalview of the display panel taken along line IV-IV′ of FIG. 3 at thisstep. FIG. 24A and FIG. 24B are sectional views of the display paneltaken along lines XXIVA-XXIVA′ and XXIVB-XXIVB′ of FIG. 23,respectively, and FIG. 24C is a sectional view of the display paneltaken along line IV-IV′ of FIG. 3 at this step. FIG. 26A and FIG. 26Bare sectional views of the display panel taken along lines XXVIA-XXVIA′and XXVIB-XXVIB′ of FIG. 25, respectively, and FIG. 26C is a sectionalview of the display panel taken along line IV-IV′ of FIG. 3 at thisstep. FIG. 27A and FIG. 27B are sectional views of the display paneltaken along lines XXVIA-XXVIA′ and XXVIB-XXVIB′ of FIG. 25,respectively, and illustrate a step following the step shown in FIG. 26Aand FIG. 26B, and FIG. 27C is a sectional view of the display paneltaken along line IV-IV′ of FIG. 3 at this step.

Referring to FIGS. 9-10C, a blocking layer 111 is formed on aninsulating substrate 110, and a semiconductor layer made of a-Si may bedeposited on the blocking layer 111 by LPCVD (low pressure chemicalvapor deposition), PECVD (plasma enhanced chemical vapor deposition) orsputtering.

Next, the semiconductor layer may be crystallized into polysilicon andphoto-etched to form a plurality of pairs of first and secondsemiconductor islands 151 a and 151 b. Alternatively, the semiconductorlayer may be left as an a-Si layer.

Referring to FIGS. 11-12C, a gate insulating layer 140 and a gate metallayer are sequentially deposited on the substrate including the firstand second semiconductor islands 151 a and 151 b, and a firstphotoresist PR1 is formed thereon. The gate metal layer is etched byusing the first photoresist PR1 as an etch mask to form a plurality ofgate electrodes 124 b, including storage electrodes 127, and a pluralityof gate metal members 120 a. A P-type impurity is introduced intoportions of the second semiconductor islands 151 b, which are notcovered with the gate electrodes 124 b and the gate metal members 120 aas well as the first photoresist PR1, to form a plurality of P-typeextrinsic regions 153 b and 155 b. At this time, the first semiconductorislands 151 a are covered with the first photoresist PR1 and the gatemetal members 120 a and protected from impurity implantation.

Referring to FIGS. 13-14C, the first photoresist PR1 is removed, and asecond photoresist PR2 is formed. The gate metal members 120 a areetched using the second photoresist PR2 as an etch mask to form aplurality of gate lines 121 including gate electrodes 124 a. An N-typeimpurity is injected into portions of the first semiconductor islands151 a, which are not covered with the gate lines 121 and the gateelectrodes 124 b as well as the second photoresist PR2, to form aplurality of N-type extrinsic regions 153 a and 155 a. At this time, thesecond semiconductor islands 151 b are covered with the secondphotoresist PR2 and protected from impurity implantation.

Referring to FIGS. 15-16C, an interlayer insulating film 160 isdeposited and the interlayer insulating film 160 and the gate insulatinglayer 140 are photo-etched to form a plurality of contact holes 163 a,163 b, 165 a and 165 b exposing the extrinsic regions 153 a, 153 b, 155a and 155 b, respectively, as well as a plurality of contact holes 164exposing the gate electrodes 124 b.

Referring to FIGS. 17-18C, a plurality of data conductors including aplurality of data lines 171, which include first source electrodes 173a, a plurality of driving voltage line 172, which include second sourceelectrodes 173 b, a plurality of first and second drain electrodes 175 aand 175 b, and a common voltage line 278 are formed on the interlayerinsulating layer 160.

Referring to FIGS. 19-20C, a passivation layer 180 is deposited andphoto-etched to form a plurality of contact holes 185 and 188 exposingthe second drain electrodes 175 b and the common voltage line 278,respectively.

Referring to FIGS. 21-22C, a plurality of pixel electrodes 190 and acontact assistant 88 are formed on the passivation layer 180. When thepixel electrodes 190 are made of a reflective opaque material, they maybe formed of the data metal layer along with the data lines 171.

Referring to FIGS. 23-24C, an insulating layer is deposited andpatterned to form a partition 360 having a plurality of openings 365 onthe pixel electrodes 190 and having at least one contact hole 368 on thecontact assistant 88.

Referring to FIGS. 25-26C, a plurality of organic light emitting members370 including at least a light emitting layer, and which may furtherinclude multiple layers, are formed in the openings 365 by deposition orinkjet printing following a masking.

Referring to FIGS. 27A-27C, a lower electrode 271 is formed by using ashadow mask, etc., such that the lower electrode 271 is not arranged onthe contact hole 368.

An upper electrode 272, having a contact portion B arranged on thecontact hole 368, is formed on the lower electrode 271 as shown in FIG.3, FIG. 4, FIG. 6 and FIG. 7. Although not shown, the OLED device maythen be sealed by, for example, a sealing film or a metal cap.

It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. A display panel for an organic light emitting display, the panelcomprising: a plurality of anode electrodes; a cathode electrode that issupplied with a predetermined voltage and includes a first portionfacing the anode electrodes and a second portion receiving thepredetermined voltage and having a different cross-section than thefirst portion; a plurality of light emitting members arranged betweenthe anode electrodes and the cathode electrode; and a conductive linetransmitting the predetermined voltage and contacting the second portionof the cathode electrode.
 2. The display panel of claim 1, wherein thefirst portion comprises a multiple-layered portion.
 3. The display panelof claim 2, wherein the multiple-layered portion comprises a first layercontacting the light emitting members and a second layer, the firstlayer being arranged between the anode electrodes and the second layer.4. The display panel of claim 3, wherein the first layer is spaced apartfrom the conductive line.
 5. The display panel of claim 4, wherein thesecond portion comprises the second layer.
 6. The display panel of claim5, wherein the first layer has a lower work function than the secondlayer.
 7. The display panel of claim 6, wherein the first layercomprises an alkali metal or an alkali earth metal.
 8. The display panelof claim 7, wherein the first layer comprises Ba, Ca, or Li.
 9. Thedisplay panel of claim 5, wherein the first layer comprises LiF.
 10. Thedisplay panel of claim 5, wherein the second layer has a lowerresistivity than the first layer.
 11. The display panel of claim 5,wherein the first layer is more oxidizable than the second layer. 12.The display panel of claim 1, wherein the conductive line has amultiple-layered structure.
 13. A display panel for an organic lightemitting display, the panel comprising: a plurality of anode electrodes;a plurality of light emitting members arranged on the anode electrodes,respectively; a metal layer including a first portion arranged on thelight emitting members and a second portion spaced apart from the lightemitting members; and a conductive line coupled to the second portion ofthe metal layer, wherein the conductive line is arranged on a layer thatis beneath a layer that the light emitting members are arranged on. 14.The display panel of claim 13, further comprising an insulating layerarranged on the conductive line and under the light emitting members.15. The display panel of claim 14, wherein the insulating layer isarranged under the anode electrodes and has a contact hole exposing theconductive line at least in part.
 16. The display panel of claim 15,further comprising a contact assistant arranged between the conductiveline and the metal layer.
 17. The display panel of claim 16, wherein theanode electrodes comprise a transparent material.
 18. The display panelof claim 17, wherein the contact assistant is arranged on the same layeras the anode electrodes.
 19. The display panel of claim 13, furthercomprising: a scanning line; a data line; a switching transistor coupledto the scanning line and the data line; a driving transistor coupled tothe switching transistor and an anode electrode; and a capacitor coupledbetween terminals of the driving transistor.
 20. The display panel ofclaim 19, wherein the conductive line comprises the same layer as one ofthe scanning line and the data line.